STD25NF10LA

STD25NF10LA N-channel 100 V, 0.030 Ω, 25 A DPAK STripFET™ II Power MOSFET Features Order code VDSS RDS(on) max ID STD25NF10LA 100 V < 0.035 Ω 25 A ■ Exceptional dv/dt capability ■ 100% avalanche tested ■ Logic level device TAB 3 1 DPAK Applications ■ Switching application ■ Automotive Description Figure 1. This Power MOSFET has been developed using STMicroelectronics’ unique STripFET process, which is specifically designed to minimize input capacitance and gate charge. This renders the device suitable for use as primary switch in advanced high-efficiency isolated DC-DC converters for telecom and computer applications, and applications with low gate charge driving requirements. Internal schematic diagram D(TAB) G(1) S(3) Table 1. AM09016v1 Device summary Order code Marking Package Packaging STD25NF10LA D25NF10LA DPAK Tape and reel October 2011 Doc ID 022319 Rev 1 1/15 www.st.com 15 Contents STD25NF10LA Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 ................................................ 8 Doc ID 022319 Rev 1 STD25NF10LA 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate- source voltage ± 16 V Drain current (continuous) at TC = 25 °C 25 A Drain current (continuous) at TC = 100 °C 21 A Drain current (pulsed) 100 A Total dissipation at TC = 25 °C 100 W Derating Factor 0.67 W/°C ID (1) ID IDM (2) Ptot (3) Peak diode recovery avalanche energy 20 V/ns (4) Single pulse avalanche energy 450 mJ -55 to 175 °C dv/dt EAS Tstg Tj Storage temperature Max. operating junction temperature 1. Current limited by package 2. Pulse width limited by safe operating area. 3. ISD ≤25 A, di/dt ≤300 A/µs, VDD =V(BR)DSS, TJ ≤TJMAX 4. Starting Tj = 25 °C, ID = 12.5 A VDD = 50 V Table 3. Symbol Rthj-case Rthj-pcb Thermal data Parameter Thermal resistance junction-case max Thermal resistance junction-pcb max (1) Value Unit 1.5 °C/W 50 °C/W 1. When Mounted on 1 inch2 FR-4 board, 2 oz. of Cu. Doc ID 022319 Rev 1 3/15 Electrical characteristics 2 STD25NF10LA Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 250 µA, VGS =0 IDSS Zero gate voltage drain current VDS= 100 V VDS= 100 V, TC = 125 °C VGS =0 IGSS Gate-body leakage current VGS = ± 16 V, VDS = 0 VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS = 10 V, ID = 12.5 A VGS = 4.5 V, ID = 12.5 A Table 5. Symbol 4/15 Test conditions Min. Typ. Max. 100 Unit V 1 10 µA µA ±100 nA 2.5 V 0.030 0.035 0.035 0.040 Ω Ω Min. Typ. Max. Unit - 1710 250 110 pF pF pF ns ns ns ns 1 Dynamic Parameter Test conditions Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25 V, f = 1 MHz, VGS = 0 td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 50 V, ID = 12.5 A RG = 4.7 Ω VGS = 5 V (see Figure 13) - 20 40 58 20 Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 80 V, ID = 25 A, VGS = 5 V, RG = 4.7 Ω (see Figure 14) - 38 8.5 21 Doc ID 022319 Rev 1 52 nC nC nC STD25NF10LA Electrical characteristics Table 6. Source drain diode Symbol Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current trr Qrr IRRM Test conditions Min. Typ. Max. Unit - 25 100 A A ISD = 25 A, VGS = 0 - 1.5 V ISD = 25 A, di/dt = 100 A/µs, VDD = 50 V, Tj = 150 °C (see Figure 15) - 88 317 7.2 ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 022319 Rev 1 5/15 Electrical characteristics STD25NF10LA 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized breakdown voltage vs. temperature Figure 7. Static drain-source on resistance 6/15 Doc ID 022319 Rev 1 STD25NF10LA Figure 8. Electrical characteristics Gate charge vs. gate-source voltage Figure 9. Figure 10. Normalized gate threshold voltage vs. temperature Capacitance variations Figure 11. Normalized on resistance vs. temperature Figure 12. Source-drain diode forward characteristics Doc ID 022319 Rev 1 7/15 Test circuit 3 STD25NF10LA Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 17. Unclamped inductive waveform AM01471v1 Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/15 0 Doc ID 022319 Rev 1 10% AM01473v1 STD25NF10LA 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 022319 Rev 1 9/15 Package mechanical data Table 7. STD25NF10LA DPAK (TO-252) mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 1.50 L1 2.80 L2 0.80 L4 0.60 R V2 10/15 Typ. 1 0.20 0° 8° Doc ID 022319 Rev 1 STD25NF10LA Package mechanical data Figure 19. DPAK (TO-252) drawing 0068772_H Figure 20. DPAK footprint(a) 6.7 1.8 3 1.6 2.3 6.7 2.3 1.6 AM08850v1 a. All dimensions are in millimeters Doc ID 022319 Rev 1 11/15 Packing mechanical data 5 STD25NF10LA Packing mechanical data Table 8. DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 12/15 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 Doc ID 022319 Rev 1 18.4 22.4 STD25NF10LA Packing mechanical data Figure 21. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 W K0 B0 For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 Figure 22. Reel for DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At sl ot location B D C N A Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Doc ID 022319 Rev 1 13/15 Revision history 6 STD25NF10LA Revision history Table 9. 14/15 Revision history Date Revision 05-Oct-2011 1 Changes First release. Doc ID 022319 Rev 1 STD25NF10LA Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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