STL12N65M2

STL12N65M2 Datasheet N-channel 650 V, 0.62 Ω typ., 5 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 5x6 HV package Features 1 2 3 4 PowerFLAT 5x6 HV D(5, 6, 7, 8) 8 7 Order code VDS RDS(on) max. ID PTOT STL12N65M2 650 V 0.75 Ω 5A 48 W • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected 5 6 Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) AM15540v1 This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL12N65M2 Product summary Order code STL12N65M2 Marking 12N65M2 Package PowerFLAT™ 5x6 HV Packing Tape and reel DS11049 - Rev 2 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL12N65M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 5 Drain current (continuous) at Tcase = 100 °C 3.2 IDM (1) Drain current (pulsed) 20 A PTOT Total power dissipation at Tcase = 25 °C 48 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range ID Tj Operating junction temperature range A V/ns -55 to 150 °C 1. Pulse width is limited by safe operating area. 2. ISD ≤ 5 A, di/dt ≤ 400 A/μs; VDS (peak) ≤ V(BR)DSS, VDD = 400 V. 3. VDS ≤ 520 V. Table 2. Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case 2.6 Rthj-pcb (1) Thermal resistance junction-pcb 50 Unit °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR (1) EAS (2) Parameter Value Unit Avalanche current, repetitive or not repetitive 1.2 A Single pulse avalanche energy 105 mJ 1. Pulse width limited by Tjmax. 2. starting Tj = 25 °C, ID = IAR, VDD = 50 V. DS11049 - Rev 2 page 2/15 STL12N65M2 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4. Static Symbol Parameter V(BR)DSS Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 650 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = 25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 3 A VGS = 0 V, VDS = 650 V, Tcase = 125 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1 °C(1) 100 2 µA ±10 µA 3 4 V 0.62 0.75 Ω 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Reverse transfer capacitance (1) Min. Typ. Max. Unit - 410 - - 20 - - 0.9 - pF Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 43 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.4 - Ω Qg Total gate charge - 12.5 - Qgs Gate-source charge - 3.2 - Qgd Gate-drain charge - 5.8 - Coss eq. VDD = 520 V, ID = 7 A, VGS = 0 to 10 V (see Figure 14 ) nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol Parameter td(on) Turn-on delay time - 9.5 - Rise time VDD = 325 V, ID = 3.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 13 and Turn-off delay time Figure 18) - 7.5 - - 26 - Fall time - 15 - tr td(off) tf DS11049 - Rev 2 Test conditions Min. Typ. Max. Unit ns page 3/15 STL12N65M2 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5 A ISDM (1) Source-drain current (pulsed) - 20 A - 1.6 V VSD (2) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr VGS = 0 V, ISD = 5 A ISD = 7 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15) Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 7 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15) - 318 ns - 2.5 µC - 15.5 A - 437 ns - 3.2 µC - 15 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS11049 - Rev 2 page 4/15 STL12N65M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance GIPG110515MQF1LSOA ID (A) K ZthPowerFlat_5x6_19 d=0.5 0.2 10 1 10 0 10 -1 ) S( on 1 ms 10 ms 10 0 V DS (V) 10 2 10 1 Figure 3. Output characteristics ID (A) 10-2 V GS = 7 V 10-3 -6 10 10-5 10-4 10-3 10-2 10-1 100 tp(s) Figure 4. Transfer characteristics GIPG110515MQF1LTCH 12 10 V DS = 19 V 10 V GS = 6 V 8 8 6 6 4 4 2 0 0 4 8 12 V GS = 5 V 2 16 0 0 V DS (V) Figure 5. Gate charge vs gate-source voltage GIPG110515MQF1LQVG VDS VGS (V) (V) VDS 600 VDD = 520 V ID = 7 A 10 400 6 300 4 200 2 100 2 4 6 8 2 4 6 8 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (Ω) GIPG110515MQF1LRID V GS = 10 V 0.66 500 8 0 0 Single pulse ID (A) GIPG110515MQF1LOCH V GS = 8,9,10 V 12 12 0.05 0.02 0.01 T j ≤ 150 °C T c = 25 °C single pulse 10 -2 10 -1 DS11049 - Rev 2 10 0.1 100 μs D O lim per ite ati d on by in m th ax is . R ar e a is 10 μs -1 10 12 0 Qg (nC) 0.64 0.62 0.60 0.58 0 1 2 3 4 5 I D (A) page 5/15 STL12N65M2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG110515MQF1LCVR V GS(th) (norm.) 10 3 GIPG110515MQF1LVTH I D = 250 µA 1.1 C ISS 1.0 10 2 C OSS 10 1 0.9 0.8 f = 1 MHz 10 0 C RSS 0.7 10 -1 10 -1 10 0 10 1 0.6 -75 V DS (V) 10 2 Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) GIPG110515MQF1LRON V GS = 10 V 2.2 1.00 1.0 0.96 0.6 0.92 75 125 T j (°C) Figure 11. Output capacitance stored energy E OSS (μJ) GIPG110515MQF1LEOS 125 I D = 1 mA 0.88 -75 -25 25 75 125 T j (°C) Figure 12. Source- drain diode forward characteristics V SD (V) GIPG110515MQF1LSDF 1.2 3 T j (°C) GIPG110515MQF1LBDV 1.08 1.4 25 75 V (BR)DSS (norm.) 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 T j = -55 °C 1.0 T j = 25 °C 0.8 T j = 150 °C 2 0.6 0.4 1 0.2 0 0 DS11049 - Rev 2 100 200 300 400 500 600 V DS (V) 0.0 0 1 2 3 4 5 I SD (A) page 6/15 STL12N65M2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11049 - Rev 2 page 7/15 STL12N65M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS11049 - Rev 2 page 8/15 STL12N65M2 PowerFLAT 5x6 HV package information 4.1 PowerFLAT 5x6 HV package information Figure 19. PowerFLAT 5x6 HV package outline 8368143_Rev_4 DS11049 - Rev 2 page 9/15 STL12N65M2 PowerFLAT 5x6 HV package information Table 8. PowerFLAT 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS11049 - Rev 2 page 10/15 STL12N65M2 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS11049 - Rev 2 page 11/15 STL12N65M2 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS11049 - Rev 2 page 12/15 STL12N65M2 Revision history Table 9. Document revision history DS11049 - Rev 2 Date Revision Changes 11-May-2015 1 First release. 20-Jun-2019 2 Updated Section 1 and Section 2 page 13/15 STL12N65M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS11049 - Rev 2 page 14/15 STL12N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS11049 - Rev 2 page 15/15