STL86N3LLH6AG

STL86N3LLH6AG Datasheet Automotive-grade N-channel 30 V, 4 mΩ typ., 80 A STripFET™ H6 Power MOSFET in a PowerFLAT™ 5x6 package Features 2 1 3 8 7 VDS RDS(on) max. ID STL86N3LLH6AG 30 V 5.2 mΩ 80 A 4 PowerFLAT™ 5x6 D(5, 6, 7, 8) Order code 5 6 • • • • • • • AEC-Q101 qualified Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Logic level Wettable flank package G(4) Applications 1 2 3 4 • Switching applications Top View S(1, 2, 3) AM15540v2 Description This device is an N-channel Power MOSFET developed using the STripFET™ H6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Product status link STL86N3LLH6AG Product summary Order code STL86N3LLH6AG Marking 86N3LLH6 Package PowerFLAT™ 5x6 Packing Tape and reel DS10615 - Rev 5 - February 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL86N3LLH6AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ± 20 V ID (1) Drain current (continuous) at TC = 25 °C 80 A (1) Drain current (continuous) at TC = 70 °C 60 A Drain current (continuous) at TC = 100 °C 51 A ID ID (1) IDM , (2) (1) Drain current (pulsed) 320 A (3) Drain current (continuous) at Tpcb = 25 °C 21 A ID (3) Drain current (continuous) at Tpcb = 70 °C 15.7 A ID (3) Drain current (continuous) at Tpcb = 100 °C 13.1 A Drain current (pulsed) 84 A Total power dissipation at TC = 25 °C 60 Total power dissipation at Tpcb = 25 °C 4 ID IDM, (2) (3) PTOT (1) PTOT (3) Tstg Storage temperature range Tj Operating junction temperature range - 55 to 150 W °C 1. The value is rated according to Rthj-c.. 2. Pulse width limited by safe operating area. 3. The value is rated according to Rthj-pcb.. Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Thermal resistance junction-case 2.08 Thermal resistance junction-pcb 31.3 Unit °C/W 1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s DS10615 - Rev 5 page 2/17 STL86N3LLH6AG Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified). Table 3. On/off-states Symbol V(BR)DSS IDSS IGSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Zero gate voltage VGS = 0 V, VDS = 30 V drain current Gate-body leakage current VGS(th) Gate threshold voltage RDS(on) Static drain-source onresistance VGS = 0 V, VDS = 30 V, TC = 125 Min. Typ. Max. 30 Unit V 1 °C(1) 10 VDS = 0 V, VGS = ± 20 V µA ±100 nA 1.7 2.5 V VGS = 10 V, ID = 10.5 A 4 5.2 mΩ VGS = 4.5 V, ID = 10.5 A 6.7 7.6 mΩ Min. Typ. Max. Unit 1350 1690 2030 pF 230 290 350 pF 140 176 210 pF VDS = VGS, ID = 250 µA 1 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 15 V, ID = 21 A, - 17 - nC Qgs Gate-source charge VGS = 0 to 4.5 V - 8 - nC Qgd Gate-drain charge (see Figure 12. Test circuit for resistive load switching times) - 6 - nC RG Gate input resistance f = 1 MHz, ID = 0 A 1.25 1.7 1.2 Ω Min. Typ. Max. Unit VDS = 25 V, f = 1 MHz, VGS = 0 V Table 5. Switching times Symbol td(on) tr td(off) tf DS10615 - Rev 5 Parameter Test conditions Turn-on delay time VDD = 15 V, ID = 10.5 A, - 9.5 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 30 - ns Turn-off delay time See Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform - 37 - ns - 12 - ns Fall time page 3/17 STL86N3LLH6AG Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 21 A Source-drain current (pulsed) - 84 A 1.1 V Forward on voltage ISD = 21 A, VGS = 0 V - trr Reverse recovery time ISD = 10.5 A, di/dt = 100 A/µs - 24 ns Qrr Reverse recovery charge VDD = 25 V - 16.8 nC Reverse recovery current See Figure 14. Test circuit for inductive load switching and diode recovery times - 1.4 A VSD IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%. DS10615 - Rev 5 page 4/17 STL86N3LLH6AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance K GIPG270920161304SOA Operation in this area is limited by RDS(on) GIPG270920161305ZTH δ=0.3 DS(on) 10 µs 20 µs 50 µs 100 δ=0.2 δ=0.1 100 µs 10 0.05 10 -1 1 ms 1 TC= 25 °C TJ = 150 °C Single pulse 0.1 0.1 10 ms 1 V DS (V) 10 Figure 3. Output characteristics ID (A) 10 -4 10 -3 AM08916v1 ID (A) VDS=3 V 6V 250 t p (s) 10 -2 Figure 4. Transfer characteristics AM08915v1 VGS=10 V 10 -2 10 -5 200 5V 200 150 150 4V 100 100 50 0 0 DS10615 - Rev 5 3V 1 2 3 4 5 VDS(V) 50 0 0 1 2 3 4 5 VGS(V) page 5/17 STL86N3LLH6AG Electrical characteristics (curves) Figure 5. Normalized V(BR)DSS vs temperature AM08917v1 V(BR)DSS (norm) 1.06 ID=1 mA 1.04 Figure 6. Static drain-source on-resistance 4.5 1.00 4.0 0.98 3.5 0.96 3.0 0.94 2.5 0 25 50 TJ(°C) 75 100 Figure 7. Gate charge vs gate-source voltage AM08919v1 VGS (V) VDD=15V ID=21A 12 VGS=10V 5.0 1.02 0.92 -50 -25 AM08918v1 RDS(on) (mW) 5.5 2.0 20 10 0 30 ID(A) Figure 8. Capacitance variations AM08920v1 C (pF) 2500 10 2000 8 Ciss 1500 6 1000 4 500 2 Coss Crss 0 0 20 10 30 40 50 Qg(nC) Figure 9. Normalized gate threshold voltage vs temperature AM08921v1 VGS(th) (norm) 0 0 10 20 VDS(V) Figure 10. Normalized on resistance vs temperature AM08922v1 RDS(on) (norm) 1.8 ID=250µA 1.2 ID=10.5A VGS=10V 1.6 1.4 1.0 1.2 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 -50 -25 DS10615 - Rev 5 0.2 0 25 50 75 100 TJ(°C) 0 -50 -25 0 25 50 75 100 TJ(°C) page 6/17 STL86N3LLH6AG Electrical characteristics (curves) Figure 11. Source-drain diode forward characteristics AM08923v1 VSD (V) 1.0 TJ=-55°C 0.9 0.8 TJ=25°C TJ=150°C 0.7 0.6 0.5 0.4 0 DS10615 - Rev 5 10 20 30 40 50 60 70 ISD(A) page 7/17 STL86N3LLH6AG Test circuits 3 Test circuit Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10615 - Rev 5 page 8/17 STL86N3LLH6AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS10615 - Rev 5 page 9/17 STL86N3LLH6AG PowerFLAT™ 5x6 WF type R package information 4.1 PowerFLAT™ 5x6 WF type R package information Figure 18. PowerFLAT™ 5x6 WF type R package outline 8231817_R_WF_Rev_18 DS10615 - Rev 5 page 10/17 STL86N3LLH6AG PowerFLAT™ 5x6 WF type R package information Table 7. PowerFLAT™ 5x6 WF type R mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.10 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.10 D5 0.25 0.4 0.55 D6 0.15 0.3 0.45 e DS10615 - Rev 5 Typ. 0.50 4.45 1.27 E 6.20 6.40 6.60 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.85 1.00 1.15 E9 4.00 4.20 4.40 E10 3.55 3.70 3.85 K 1.275 L 0.725 0.825 0.925 L1 0.175 0.275 0.375 ϴ 0° 1.575 12° page 11/17 STL86N3LLH6AG PowerFLAT™ 5x6 WF type R package information Figure 19. PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_rev18 DS10615 - Rev 5 page 12/17 STL86N3LLH6AG PowerFLAT™ 5x6 WF packing information 4.2 PowerFLAT™ 5x6 WF packing information Figure 20. PowerFLAT™ 5x6 WF tape (dimensions are in mm) 1.50 +0.1 0.0 Po 4.0 0.1(II) P2 2.0 0.05(I) E1 1.75 0.1 Y F(5.50±0.0.05)(III) Do Bo (5.35±0.05) D1 1.50 MIN R0.30 MAX Ko (1.20±0.1) W(12.00±0.1) T 0.30 0.05 Y P1(8.00±0.1) Ao(6.70±0.1) SECTION Y-Y (I) (II) (III) Measured from centreline of sprocket hole to centreline of pocket. Cumulative tolerance of 10 sprocket holes is ± 0.20 . Measured from centreline of sprocket hole to centreline of pocket. Base and bulk qua ntity 3000 pcs 8234350_TapeWF_rev_C Figure 21. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification DS10615 - Rev 5 page 13/17 STL86N3LLH6AG PowerFLAT™ 5x6 WF packing information Figure 22. PowerFLAT™ 5x6 reel (dimensions are in mm) R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ∅4.00 ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) ∅2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters ∅13.00 CORE DETAIL DS10615 - Rev 5 8234350_Reel_rev_C page 14/17 STL86N3LLH6AG Revision history Table 8. Document revision history Date Revision 26-Sep-2014 1 21-Jan-2015 2 03-Feb-2015 3 03-Oct-2016 4 Changes First release. Document status promoted from preliminary to production data. Updated Section 4: Package mechanical data. Updated title and features in cover page. Updated title and features in cover page. Updated Table 1. Absolute maximum ratings and Table 3. On/off-states. Changed Figure 1. Safe operating area and Figure 2. Thermal impedance. 11-Feb-2019 DS10615 - Rev 5 5 Updated Section 4 Package information Minor text changes. page 15/17 STL86N3LLH6AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 PowerFLAT™ 5x6 WF type R package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 PowerFLAT™ 5x6 WF packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS10615 - Rev 5 page 16/17 STL86N3LLH6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS10615 - Rev 5 page 17/17